Geek out over all things technology and start-up in Taipei.

Driving innovation in Taipei's tech scene

Launch your next venture or expand your network within Taipei

Taipei Tech Forum

The Most Important Thing

Currently, all of TSMC's CoWoS capacity is in Taiwan.  Would a move like this diminish Taiwan’s silicon shield? 

https://www.reuters.com/technology/tsmc-considering-advanced-chip-packaging-capacity-japan-sources-say-2024-03-17/
#Taipei Tech Forum

Currently, all of TSMC's CoWoS capacity is in Taiwan.  Would a move like this diminish Taiwan’s silicon shield?   https://www.reuters.com/technology/tsmc-considering-advanced-chip-packaging-capacity-japan-sources-say-2024-03-17/ #Taipei Tech Forum

Nate

The Biden administration is initiating a $1.6B funding competition focused on chip packaging R&D as part of the 2022 Chips and Science Act. Projects across five research domains will receive up to $150M each, aimed at advancing technologies in equipment, power management, connectors, electronic design automation, and chipset integration.

More:

Chip packaging is vital for chip protection and connectivity, with the U.S. holding just 3% of the global packaging capacity.
Most chip packaging occurs in Asia, but companies like Intel, SK Hynix, Amkor, and Samsung are establishing U.S.-based plants.
This competition is the largest funding opportunity from the $11B Chips Act R&D fund.
The Chips Act provides $39B in grants, $75B in loans and guarantees, and 25% tax credits to boost domestic semiconductor manufacturing.

https://www.bloomberg.com/news/articles/2024-07-09/us-opens-1-6-billion-competition-for-chip-packaging-research?utm_source=website&utm_medium=share&utm_campaign=copy

IIRC Most of the latest packaging machines are made by TOWA and many of TSMC's suppliers are also based in Japan:

https://asiatimes.com/2021/06/tsmc-eyes-3d-chip-packaging-edge-in-japan/

IIRC Most of the latest packaging machines are made by TOWA and many of TSMC's suppliers are also based in Japan:  https://asiatimes.com/2021/06/tsmc-eyes-3d-chip-packaging-edge-in-japan/

TOKYO - Three-dimensional integrated circuit (3D IC) packaging saves space and materials and is vastly more energy-efficient than previous 2D technology.

TSMC eyes 3D chip packaging edge in Japan - Asia Times

Todd Smith

The Biden administration is initiating a $1.6B funding competition focused on chip packaging R&D as part of the 2022 Chips and Science Act. Projects across five research domains will receive up to $150M each, aimed at advancing technologies in equipment, power management, connectors, electronic design automation, and chipset integration.  More:  Chip packaging is vital for chip protection and connectivity, with the U.S. holding just 3% of the global packaging capacity. Most chip packaging occurs in Asia, but companies like Intel, SK Hynix, Amkor, and Samsung are establishing U.S.-based plants. This competition is the largest funding opportunity from the $11B Chips Act R&D fund. The Chips Act provides $39B in grants, $75B in loans and guarantees, and 25% tax credits to boost domestic semiconductor manufacturing.  https://www.bloomberg.com/news/articles/2024-07-09/us-opens-1-6-billion-competition-for-chip-packaging-research?utm_source=website&utm_medium=share&utm_campaign=copy

The Biden administration is launching a $1.6 billion funding competition for chip packaging research and development projects, marking the latest attempt to revitalize the domestic semiconductor industry.

Nate

Currently, all of TSMC's CoWoS capacity is in Taiwan. Would a move like this diminish Taiwan’s silicon shield? https://www.reuters.com/t.. #Taipei Tech Forum